module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done,
    output [7:0] out_byte
); 
    reg [3:0] state;
    reg [3:0] next_state;
    reg [7:0] in_byte;
    reg checkbyte;
    reg odd;
    reg checkreset;
    parameter Dstart = 0,D0=1,D1=2,D2=3,D3=4;
    parameter D4=5,D5=6,D6=7,D7=8,Dstop=9,Dw=10,De=11,check=12;

    parity pa(clk,checkreset,in,odd);
    always @(*) begin
        case (state)
            Dstart:begin
                next_state=D0;
                in_byte[0]=in;
                checkreset=0;
                checkbyte=in; 
                
            end
            
            D0:begin
               next_state=D1;
               in_byte[1]=in; 
               checkbyte=in; 
            end
            
            D1:begin
               next_state=D2;
                in_byte[2]=in; 
                checkbyte=in; 
            end
            D2:begin
               next_state=D3;
              in_byte[3]=in; 
              checkbyte=in; 
            end
            D3:begin
               next_state=D4;
               in_byte[4]=in;
               checkbyte=in; 
            end
            D4:begin
               next_state=D5;
               in_byte[5]=in;  
               checkbyte=in; 
            end
            D5:begin
               next_state=D6;
               in_byte[6]=in;
               checkbyte=in; 
            end 
            D6:begin
               next_state=D7;
                in_byte[7]=in;
                checkbyte=in; 
            end 
            D7:begin
               next_state=check;
                checkbyte=in;
            end            
            Dstop:begin
                next_state=in?Dw:Dstart;
            end
            
            De:next_state=in?Dw:De;

            Dw:begin
                next_state=in?Dw:Dstart;
            end

            check:begin
                if (odd==1) begin
                    next_state=in?Dstop:De;
                end else begin
                    next_state=De;
                end
            end
            
        endcase
    end

    always @(posedge clk ) begin
        if (reset==1) begin
            state<=Dw;
        end else begin
            state<=next_state;
            if (state==Dstop) begin
               
            end
        end
    end

    assign done=(state==Dstop);
    assign out_byte=in_byte;


endmodule
